A multilayer PCB usually comprises a number of planar conductor layers used for signal, ground and power supplies where the conductor layers are isolated by a material. Planar interconnect circuits embedded in the PCB can be developed on the base of transmission lines such as microstrip lines, strip lines, coplanar lines, and slot lines which have typically low leakage losses and well-defined characteristic impedance. These properties of planar transmission lines give a possibility to develop high-performance and matched interconnections based on PCB technologies. Vertical transitions in the PCB which serve to connect planar interconnected circuits disposed at the different conductor layers are usually based on various types of via structures such as through hole vias, blind vias, counter-bored, and buried vias (see Patent Document No. 1). These transitions have usually poor-defined wave guiding properties that leads to problems in controlling characteristic impedance and high leakage, especially, at higher frequencies.
As a solution to improve guiding and shielding properties of vertical transitions in multilayer PCBs at higher frequencies, ground vias surrounding a signal via can be used. Such ground vias are usually connected to ground planes of the multilayer PCB. As a rule, a multilayer PCB includes power supply planar conductor layers. To provide passages of ground vias through power supply layers the clearance hole isolating each ground via and the power supply plane is usually used around each ground via (see Patent Document Nos. 2-8).
Referring to the drawings, a signal via 101 in a 12-conductor-layer PCB, which serves only as an example of multilayer PCB design, is shown in FIGS. 1A and 1B. FIG. 1B shows a cross-sectional view of a vertical transition (in a direction of a dotted line 1B in FIG. 1A), the arrangement of conductor layers of the PCB separated by an isolating material is as follows: Ground planes are 2nd, 4th, 6th, 7th, 9th, and 11th layers; Power supply plane is 5th layer; Signal planes are 1st, 3rd, 8th, 10th, and 12th layers. The signal via is separated from conductor planes of the PCB by a clearance hole 103.
FIG. 1A shows a top view of a power supply layer which is 5th layer of a vertical transition.
At higher frequencies the single signal via 101 through clearance hole 103 has high leakage loss which degrades the electrical performance of this vertical interconnection. To decrease leakage loss ground via fence (a group of ground vias) 1021 which comprises a plurality of ground vias (see FIG. 3) surrounding the signal via 101 can be used. In this case ground vias 102 passing through the ground planes are electrically connected to these planes. At the power supply layer (5th layer in considered example) to prevent electrical contact between ground vias 102 and power supply layer 109 the clearance hole 104 can be formed around each ground via 102.
It is well-known that in a multilayer PCB parallel-plate modes can excite between conductor planes including space between power supply and ground layers. Conducting planes (power supply plane (power supply layer) 109 and ground plane (ground plate) 108 in present example shown in FIG. 2) of a multilayer PCB or a package can form a parallel-plate waveguide in which guided modes (waves) can exist. The fundamental mode of the parallel-plate waveguide is a Transverse Electromagnetic Mode or TEM mode which can propagate at all frequencies. The electric field of the TEM mode is normal to the planes (in the x direction) so that the associated magnetic field is parallel to the planes (in the y direction). The parallel-plate modes (PPMs) can resonate with via structures and also with edges of the PCB 110 (or package). Due to such resonances the electrical performance of a signal via can make worse considerably. The application of ground via fence 1021 around the signal via as shown in FIG. 3 and using the clearance hole around each ground via are ways to prevent the signal via from the parallel-plate mode resonance effect.    Patent Document No. 1: Specification of U.S. Pat. No. 6,670,559    Patent Document No. 2: Specification of U.S. Pat. No. 6,747,216    Patent Document No. 3: Specification of US Patent Application Publication No. 2003/0091730    Patent Document No. 4 Japanese Patent Application Publication No. 2000-183582    Patent Document No. 5 Japanese Patent Application Publication No. 2001-135899    Patent Document No. 6 Japanese Patent Application Publication No. 2003-100941    Patent Document No. 7 Japanese Patent Application Publication No. 10-041630    Patent Document No. 8 Japanese Patent Application Publication No. 11-054869